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VIA Technologies, Inc.
Preliminary VT6102
VT6102
PCI FAST ETHERNET CONTROLLER WITH ACPI FUNCTION
DATA SHEET
(Preliminary)
DATE :
August 1, 1999
VIA TECHNOLOGIES, INC.
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www..com
VIA Technologies, Inc.
PRELIMINARY RELEASE Please contact Via Technologies for the latest documentation.
Preliminary VT6102
Copyright Notice:
Copyright _ 1999, Via Technologies Incorporated. Printed in Taiwan. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of Via Technologies Incorporated. The VT6102 may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies. Via Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, Via Technologies assumes no responsibility for any errors in this document. Furthermore, Via Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
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Preliminary VT6102
1. OVERVIEW .................................................................. 5 1-1. VT6102 PCI FAST ETHERNET MAC CONTROLLER FEATURES..............................5 2. PINOUTS .................................................................... 6 2-1. Pin Diagram .....................................................................6 2-2. PIN LIST .........................................................................7 2-3. PIN DESCRIPTIONS .................................................................8 2-3-1. PCI Bus Interface .............................................................9 2-3-2. Network Interface ............................................................10 2-3-3. EEPROM Interface...........................................................10 2-3-4. Power Management interface..................................................11 2-3-5. Power and Ground ...........................................................11 3. FUNCTION DESCRIPTION .................................................... 12 3-1. GENNRAL DESCRIPTION ............................................................12 3-1-1. FIFO and control logic ........................................................12 3-1-2. Network interface ............................................................12 3-2. MII INTERFACE ...................................................................13 3-3. EEPROM INTERFACE .............................................................13 3-3-1. Direct Programming of EEPROM...............................................13 3-3-2. EMBEDDED PROGRAMMING OF EEPROM..........................................14 3-4. BUFFER MANAGEMENT & HOST COMMUNICATION ........................................15 3.5 BUFFER STRUCTURE AND INTERRUPT CONTROL .........................................15 3-5-1 Multiple Chained buffer structure ...............................................15 3-5-2 Interrupt Control ..............................................................16 3-5. FLOW CONTROL ..................................................................17 3-6. POWER MANAGEMENT .............................................................17 3-6-1. Wake up events .............................................................17 3-6-2. Power states ................................................................17 4. REGISTERS................................................................ 18 4-1. PCI CONFIGURATION REGISTER .....................................................18 4-1-1. PCI Configuration description (00-05H) .........................................18 4-1-2.PCI Configuration description (06-4FH) ..........................................19 4-2. VT6102 INTERNAL REGISTER MAP...................................................20 4-2-1. VT6102 internal register description (00-07H) ....................................21 4-2-2.VT6102 internal register description (08-09H) ....................................22 4-2-3. VT6102 internal register description (0C-1FH) ...................................23 4-2-4. VT6102 internal register description (20-2FH)....................................24 4-2-5. VT6102 internal register description (40-4FH)....................................25 4-2-6. VT6102 internal register description (6C-6FH) ...................................26 4-2-7. VT6102 internal register description (70-77H) ....................................27 4-2-8. VT6102 internal register description (78-7BH)....................................28 4-2-9. VT6102 internal register description (80-8BH)....................................28 4-2-10. VT6102 internal register description (8C-A7H) ..................................30 4-2-11. VT6102 internal register description (B0-FFH) ..................................31
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Preliminary VT6102
5. ELECTRICAL SPECIFICATION................................................. 32 5-1. ABSOULTE MAXIMUN RATING ........................................................32 5-2. DC SPECIFICATIONS...............................................................32 6. TIMING SPECIFICATION ...................................................... 33 6-1. PCI BUS MASTER................................................................33 6-1-1. Get TX descriptor ............................................................33 6-1-2. Get RX descriptor ............................................................34 6-1-3. Write back status to descriptor .................................................35 6-1-4. Read data into FIFO..........................................................36 6-1-5. Write data from FIFO .........................................................37 6-2. PCI BUS SLAVE .................................................................38 6-2-1. IO read/write ................................................................38 6-2-2. Cfg read/write ...............................................................39 6-3. MII ............................................................................40 6-3-1. MII TX......................................................................40 6-3-2. MII MDIO ...................................................................40 6-4. BOOTROM ......................................................................41 6-4-1. One Dword bootrom access timing (with delay transaction) ........................41 6-4-2. One Dword bootrom access timing (without delay transaction) .....................42 6-4-3. Embedded Flash Cycle Timing.................................................43 7. APPLICATION SCHEMATIC ................................................... 45 8. PACKAGE MECHANICAL SPECIFICATIONS ..................................... 47
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VIA Technologies, Inc.
Preliminary VT6102
1. Overview
1-1. VT6102 PCI FAST ETHERNET MAC CONTROLLER FEATURES
* Single chip Fast Ethernet MAC controller for PCI bus interface -- Compliant to PCI 2.2 specification. -- Provides a direct connection to PCI bus -- Supports two network ports : 10/100MB MII interface High performance PCI mastering structure -- VIA self-define 256 bytes memory I/O or register I/O based command and status register -- Software oriented chain structure description to minimize hardware complexity -- Include on chip bus master DMA with programmable burst length for high PCI bus utilization -- Support Transmit data buffer byte-alignment for low CPU utilization -- Dynamic transmit packet auto queuing for back to back transmissin -- Programmable activity polling intervals for description DMA -- Programmable DMA arbitration priority to minimize overflow under flow condition -- Support early receive and early transmit interrupt for software parallel processing -- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time -- PCI enhance command capable
*
* Provides standard 100-M bits MII interface -- Support 100Base- T4 with CAT3, CAT4, CAT 5 UTP, STP -- Support 100Base-TX with CAT5 UTP, STP and fiber cables -- 10/100Mhz full duplex, half duplex operation * Separate 2K bytes FIFO for Receive and Transmit controllers -- both supports bursts of up to full Ethernet length -- Programmable receive and transmit FIFO threshold control for optimize PCI throughput
* Flexible dynamically load EEPROM algorithm. -- Load after power-up -- Dynamic auto reload -- Embedded programming for configure modification -- Dynamic direct programming for manufacturing. * Support external Bootrom up to 64K bytes no external address latch -- Support Flash ROM read/write -- Support EPROM Read. * Support ACPI Functions -- Supports PC97, PC98, PC99 and Net PC requirements -- Supports PCI Bus Power Management Interface Specification Version 1.0/1.1 -- Supports Advanced Configuration and Power Interface (ACPI) Specification 1.0 -- Supports Network Device Class Power Management Specification Version 1.0 -- Wake-up even support link change/magic packet/ unicast physical address/MS define pattern match * Support flow control functions -- Support IEEE802.3X for full duplex. -- Support force Jam capable for half duplex. -- multiple pause frame SON/SOFF. * Single 3.3V supply, 5.0V tolerant IO 0.35um triple metal CMOS technology * 128 pin PQFP package
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VIA Technologies, Inc.
Preliminary VT6102
2. Pinouts
2-1. Pin Diagram
MRXD3 MRXD2 MRXD1 MRXD0 MRXDV MRXC SVSS SVDD MERR MTXC MTXE MTXD0 MTXD1 MTXD2 MTXD3 SVSS SVDD MCOL MCRS VDD MA15 MA14 MA13 MA12 MA11 MA10 MA9 VSS VDD RAMVSS RAMVDD MA8 MA7 MA6 MA5 MA4 VSS VDD 1 0 2 SVSS SVDD MDC MDIO VTEST AUXRST# PHYRST WOL/NC1 PME#/NC2 INTA# PCIRST# PCICLK VSS VDD GNT# REQ# AD31 AD30 AD29 AD28 VDD VSS AD27 AD26 AD25 AD24 103 105 1 0 0 9 5 9 0 8 5 8 0 7 5 7 0 6 5 64
SUSPEND WELL
60
110 55 115
VT6102
50
120 45 125 128 1 5 1 0 1 5 2 0 2 5 3 0 3 5 3 8 39
MA3 MA2 MA1 MA0 MD7 MD6 MD5 VSS VDD MD4 MD3 MD2/ECK MD1/EDI MD0/EDO BPCS BPRD# BPWR# ECS VSS VDD AD0 AD1 AD2 AD3 AD4 VSS
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CEB3# IDSEL AD23 VSS AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 VSS CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# VDD PERR# VSS PAR CBE1# AD15 AD14 AD13 AD12 AD11 AD10 VSS VDD AD9 AD8 CBE0# AD7 AD6 AD5
6
VIA Technologies, Inc. 2-2. PIN LIST
Pin Name AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 VTEST PHYRST AUXRST#
WOL/NC1 PME#/NC2
Preliminary VT6102
ECS BPCS# BPRD# BPWR#
Pin 119 120 121 122 125 126 127 128 3 5 6 7 9 10 11 12 25 26 27 28 29 30 33 34 36 37 38 40 41 42 43 44 107 109 108 110 111 47 50 49 48
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O O/D O O O O
Pin Name C/BE3# C/BE2# C/BE1# C/BE0# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# PAR PCICLK INTA# PCIRST# GNT# REQ# PERR# MA15 MA14 MA13 MA12 MA11 MA10 MA09 MA08 MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MD7 MD6 MD5 MD4 MD3 MD2/ECK MD1/EDI MD0/EDO MCRS MCOL
Pin 1 14 24 35 15 16 17 19 2 18 23 114 112 113 117 118 21 82 81 80 79 78 77 76 71 70 69 68 67 64 63 62 61 60 59 58 55 54 53 52 51 84 85
Type I I I I I/O I/O I/O I/O I I/O T/S I OD I I O I/O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I I
Pin Name MTXD3 MTXD2 MTXD1 MTXD0 MTXE MTXC MERR MRXC MRXDV MRXD3 MRXD2 MRXD1 MRXD0 MDC MDIO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SVDD SVDD SVDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SVSS SVSS SVSS RAMVDD RAMVSS
Pin 88 89 90 91 92 93 94 97 98 102 101 100 99 105 106 8 20 32 45 56 65 74 83 116 123 86 95 104 124 115 75 66 57 46 39 31 22 13 4 103 96 87 72 73
Type O O O O O I I I I I I I I O IO VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC GND
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VIA Technologies, Inc. 2-3. PIN DESCRIPTIONS
Preliminary VT6102
Signal Type Definition Type I O I/O T/S O/D Name Input Output Input / Output Tri-State Open Drain Definition Input is a standard input-only signal. This is a standard active driver. Thiis is an input/output signal Tri-stae is a bi-directional, Tri-stae input/output pin This allows multiple devices to share as a wire-OR
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VIA Technologies, Inc.
2-3-1. PCI Bus Interface No.
119-122, 125-128, 3,5,6,7,9, 10-12,25-30, 33,34,36-38 40-44
Preliminary VT6102
Name AD[31:0]
Type I/O
114 112 113
PCICLK INTA# PCIRST#
I OD I
1 14 24 35 2 15
C/BE#[3:0]
I
IDSEL FRAME#
I I/O
16
IRDY#
I/O
17
TRDY#
I/O
18
DEVSEL#
I/O
19 23
STOP# PAR
I/O T/S
117 118 21
GNT# REQ# PERR#
I O I/O
Description Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. The address phase is the clock cycle in which FRAME# is asserted. Write data is stable and valid when IRDY# is asserted and read data is stable and valid when TRDY# is asserted. PCI Clock provides timing for all transactions on PCI and is an input pin to every PCI device. Interrupt is an asynchronous signal which is used to request an interrupt PCI Rest. When PCIRST# is asserted low, the VT6102 chip performs an internal system hardware reset. PCIRST# may be asynchronous to CLK when asserted or deasserted. It is recommended that the deassertion be synchronous to guarantee clean and bounce free edge. Bus Command/Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, CBE3-0B define the Bus Command. Burring the data phase, CBE3-0B are used as Byte Enables. The Byte Enables define which physical byte lanes carry meaningful data. CBE0B applies to byte 0 and CBE3B applies to byte 3. ID Select.Used as a chip select during PCI configuration cycle. Frame:.Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase. Initiator Ready indicates the initiating agent's ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a write, IRDY# indicates that valid data is present on AD31-0. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. Target Ready indicates the target's agent's ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a read, TRDY# indicates that valid data is present on AD31-0. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. Stop: When VT6102 drives STOP# to disconnect further traction. Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Bus grant asserts to indicate to the VT6102 that access to the bus is granted. Bus request is asserted by the bus master indicate to the bus arbiter that it wants to use the bus. Parity error asserts when a data parity error is detected
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VIA Technologies, Inc.
2-3-2. Network Interface No. 85 84 88-91 92 93 Name MCOL MCRS MTXD[3:0] MTXE MTXC Type I I O O I
Preliminary VT6102
94 97 98 99-102 105
MERR MRXC MRXDV MRXD[3:0] MDC
I I I I O
106
MDIO
I/O
Description Collision detect when the external PHY device Carrier sense is asserted by the external PHY when the media is active MII 4 parallel transmit data lines. This data be synchronized to assertion by the MTXC signal Transmit enable signals that the transmit is active in the MII port to an external PHY device MII transmit clock supports the 25mhz or 2.5mhz transmit clock supplied by the external PMD device. This clock should always be active. MII receive error asserts when a data decoding error is detected by external PHY device. MII receive clock supports the 25mhz or 2.5mhz clock. This clock is recovered by the PHY. MII data valid Four parallel receive data lines. This data be driven from external PHY be synchronized with MRXC signal. MII management data clock be soured by VT86C100A MDC bit (MIIR:0) to the external PHY devices as timing reference for the MDIO signal. MII management data input/output, read from MDI bit (MIIR:1) or written from MDO bit (MIIR:2)
2-3-3. EEPROM Interface No. 47 Name ECS Type O Description EEPROM Chip Select: Chip select signal for the external EEPROM when a EEPROM is used to provide the configuration data and Ethernet Address. A 100K pull-up resistor is connected. Boot ROM Write enable, it's provides the active low output control to the flash Boot ROM Read: Read the Boot ROM on the memory support data bus. Boot ROM chip select on local memory data bus. Bootrom data bus 0 Serial ROM Data output Bootrom data bus 1 Serial ROM Data input Bootrom data bus 2 Serial ROM Clock signal Bootrom data bus [3-7]
48 49 50 51 52 53 54 55 58 59 60 82-61
BPWR# BPRD# BPCS# MD0/ EDO MD1/ EDI MD2/ ECK MD3 MD4 MD5 MD6 MD7 MA[15:0]
O O O I/O I I/O O I/O O I/O
O
Bootrom address line [15-0]
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VIA Technologies, Inc.
2-3-4. Power Management interface No. 110 111 108 Name WOL PME# AUXRST# Type O O/D I
Preliminary VT6102
109
PHYRST
O
107
VTEST
I
Description Wake on Lan Event,,programmable pulse or button WOL event, active high. Power management event.interrupt outpur PHY reset aux input. This pins might connect to PCI reset for non-wake on LAN design. This pins is normally no connect or pull up with 22 ohm resistor. PHY RESET Pin, PHY reset output to external PHY device. This output polarity control by VTEST, When VTEST=0,PHY reset high active, When VTEST=1,PHY reset low active. Test control Pin,it can control PHY reset output polarity
2-3-5. Power and Ground No. 8,20,32, 45,56,65, 74,83,1 16,123 86,95,104 4,13,22, 31,39,46, 57,66,7 5,115, 124 87,96,103 72 73 Name VDD Type P Description VCC Power: +3.3V
SVDD VSS
P G
Standby VCC Power: +3.3V Ground: 0V
SVSS RAMVDD RAMVSS
G P G
Ground: 0V Memory Interface Power Memory Interface Ground
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VIA Technologies, Inc.
Preliminary VT6102
3.FUNCTION DESCRIPTION
3-1. GENNRAL DESCRIPTION
The VT6102 ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include: twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and Early Interrupt Receive/Transmit. The VT6102 integrates the entire bus interface of PCI systems. Setting hardware jumpers or software configures the VT6102 bus interface. The VT6102 also complies with PCI Specification v2.1. The VT6102 supports the Media Independent Interface (MII) network interface.
PCI v2.1
Boot ROM
Config. EEPROM
_MSRD, _MSWR, EECS AD[31:0] PCICLK PCIRST# INTA# CBE#[3:0] IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PAR
Configuration Registers & EEPROM Control Tally Counters
PCI Bus Interface Unit
Master Registers State & Machine Buffer & Mgmt.
RxFIFO 2K bytes
TxFIFO 2K bytes
10/100M MAC Tx/Rx Protocol State
MII
TXD[3:0], RXD[3:0], TX_EN TX_ER, RX_ER TX_CLK, RX_CLK RX_DV, CRS, COL MDIO
PCI CFG
3-1-1. FIFO and control logic
The VT6102 incorporates two independent 2K bytes deeper FIFO for transmit or received data from system interface or to the network interface, providing temporary storage of data, free host system from the real-time demands on network. The VT6102 enhanced the FIFO management logic to handle received data packets up to four packets before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition latency.
3-1-2. Network interface
The VT6102 ACPI support one MII interface
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VIA Technologies, Inc. 3-2. MII INTERFACE
Preliminary VT6102
The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection between the MAC layer and PHY device. This interface has support the following characteristics: Pupport both 10M and 100M data rate. S P ontains data and synchronous clock C P-bit independent receive and transmit data. 4 PUses TTL signal levels and compatibles with common CMOS processes.
3-3. EEPROM INTERFACE
ETHER_ID1 ETHER_ID3 ETHER_ID5 Reserved SUB_SID1 SUB_VID1 Reserved Reserved Data_SEL Reserved Reserved Max_LAT BCR1 CFG_B CFG_D CHKSUM ETHER_ID0 ETHER_ID2 ETHER_ID4 MII_ PHY AD SUB_SID0 SUB_VID0 Reserved Reserved PMCC PMU_DATA_REG Reserved Min_GNT BCR0 CFG_A CFG_C 73H 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
3-3-1. Direct Programming of EEPROM The VT6102 features a easy way to program external EEPROM in-situ. When the RESET is active and if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current EEPROM has not been programmed yet. This will allow the VT6102 to enter Direct Programming mode if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per the 93C46 data sheet. To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with 73H), the user must give VT6102 a power-on reset to return to normal operation and to read in the new data. The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed in the following paragraph. For more information, refer to EECSR.
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VIA Technologies, Inc.
3-3-2. EMBEDDED PROGRAMMING OF EEPROM
Preliminary VT6102
If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct Programming mode. However, the user can still program the configuration registers A, B, and C using the Embedded Programming mode by following the routine specified in the pseudo code below. This operation will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits because these two bits return the value indifferent from the setting. This programming process is ended when the EELOAD bit goes to zero. EEPROM_EMB_PROG ( ) { // defined constant: CONFIG_B, EELOAD // declared register: value, config_for_A, config_for_B, config_for_C // declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT DISABLE_INTERRUPTS ( ); value = READ (CONFIG_B); value = value | EELOAD; WRITE (CONFIG_B, value); READ (CONFIG_B); WRITE (CONFIG_B, config_for_A); WRITE (CONFIG_B, config_for_B); WRITE (CONFIG_B, config_for_C); while (value || EELOAD) { value = READ (CONFIG_B); WAIT ( ); } ENABLE_INTERRUPTS ( ); }
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VIA Technologies, Inc. 3-4. BUFFER MANAGEMENT & HOST COMMUNICATION
Preliminary VT6102
The VT6102 provides an simply and effective buffer management and host communication method through the PCI Bus master: There are two descriptor lists, one for receive and one for transmit. The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers. The descriptor list reside in the host physical memory address space with double word boundary. And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical memory double word boundary space. The device driver can make the last descriptors next link be point to first descriptor address, become a ring buffer structure.
Buffer 1 Descriptor 0
Buffer 1
Descriptor 1
Next Descriptor
3.5 BUFFER STRUCTURE AND INTERRUPT CONTROL A data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]
3-5-1 Multiple Chained buffer structure
The VT6102 can support multiple chain buffer for direct map to OSs data buffer. The VT6102 bus mastering module will direct move the data from network to the OSs data buffer or direct transmit the data in OSs buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double word aligned. In this multiple chained buffer structure, the first data buffer's descriptor Chain
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VIA Technologies, Inc.
Preliminary VT6102
Simple Ring Buffer Structure Multiple Buffer Frame 0 F0 C F0 C F0 F0
0
F1
0
F2
0
C=DES1[15]
3-5-2 Interrupt Control
The VT6102 can controllable the receive descriptors and transmit descriptor for what the interrupt occurred. The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or saving the interrupt service overload.
C I
ER Interrupt
Here
F0 F0 F0
C I C 0 0 I
F1
Interrupt Here
C 0 0 I
Interrupt Here
F2
Save this interrupt
F3
Interrupt Here
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VIA Technologies, Inc. 3-5. FLOW CONTROL
Preliminary VT6102
The VT6102 support flow control in both half duplex and full duplex. In half duplex mode, VT6102 support jam based flow control, when traffic busy, MAC will send jam pattern. In full duplex mode, the pause frame detection logic operate base on the flow control register 0x80, if this flow control bit is set to enable, The VT6102 will detect PAUSE frame.
3-6. POWER MANAGEMENT
The VT6102 support ACPI Specification V1.0 and Network device class power management, and PC97/PC98/PC99 and net PC requirements, four wake-up evens are Support in VT6102 and can wake up the system when it received a frame that qualifies as a wake-up packet. 3-6-1. Wake up events * Link status change - If this link state have change connect or disconnect and PMEOVR bit (0x83/bit 7) enable, PME# will be generated when link state change. * Magic packet - When VT6102 is set to magic packet mode, it require that a received packet qualify as a Magic Packet The Magic packet pattern 6 FFh byte + SA duplication 16 times destination address of received magic packet matches, meanwhile Magic register (0xA0/bit 5) set enable, VT6102 will received this packed. * Unicast phisical address match - When VT6102 is set to unicast mode, it require that a received packet qualify as a unique individual address and unicast register bit (0xA0/bit 5) set enable, VT6102 will received this packed. * MS defined pattern match - IP (ARP) - Name Query - NET BIOS - VIA defined
3-6-2. Power states VT6102 Device state D0 D1,D2 D3 hot D3 cold Condition PCI=33, MAC=25M Tx,Rx Active PCI=33M, MAC=25M PCI bus transaction IDLE PCICLK IDLE, MAC=25M TX off, RX on PCI power off,MAC=25M Tx off, RX on I_PCI mA 28
18 9 9
I_AUX mA 11
9 8 8
Action From Function Any PCI transaction or interrup Wake up event Wake up event Wake up event
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VIA Technologies, Inc.
Preliminary VT6102
4.REGISTERS
4-1. PCI CONFIGURATION REGISTER
31 16 15 Device ID (3065) Status Class Code BIST Header Type 0 Vendor ID (1106) Command Revision ID Latency Timer Cache Size 00H 04H 08H 0CH 10H
Base Address Registers 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 50H 50H
Card Bus CIS Pointer(00) SUB-Vendor ID Expansion ROM Base Address Reserved Cap_Ptr Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Power Management Capabilities (PMC) Next Item Ptr Capability ID Data PMCSR_BSE Bridge Power Management Control/Status Register support Extensions (PMCSR) Reserved Rserved Reserved Rserved Reserved Rserved Reserved SUB-System ID
4-1-1. PCI Configuration description (00-05H)
OFFSET Bit 0-15 16-31 0 1 2 3 4 5 6 7 8 9 10-15 Symbol Vendor ID Device ID Command Command Command Command Command Command Command Command Command Command Command Description This field identifies the manufacturer of device. This field identifies the particular of device. IO space enable Memory space enable BUS master enable Special cycles enable Memory write and invalidate enable VGA palette snoop Parity error response Wait cycle control SERR# enable Fast back to back enable Reserved. Default 1106 3043 0 0 0 0 0 0 0 0 0 0 0 ACC RO RO RW RW RW RW RW RW RW RW RW RW RW
00-01H 02-03H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H 04-05H
Ver_01
18
VIA Technologies, Inc.
4-1-2.PCI Configuration description (06-4FH)
OFFSET 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 06-07H 08H 09-0BH 0CH 0DH 0EH 0FH 34H Bit 0-3 4 5 6 7 8 9-10 11 12 13 14 15 0-7 8-31 0-7 8-15 16-23 24-31 0-7 Symbol Status Status Status Status Status Status Status Status Status Status Status Status Revision ID Class code CacheLine Size Latency Timer Header Type BIST The Cap_Ptr
Preliminary VT6102
40H 41H
0-7 0-7
Cap ID Netx item pointer Version
42-43H
0-2
42-43H
3
PME CLK
Description Default ACC Reserved 0 RO Capabilities, such as PCI power management. 1 RO 66 MHz Capable 0 RO UDF supported 0 RO Fast back-to-back capable 1 RO Data parity error detected 0 RO DEVSEL timing ,00-fast,01-medium,10-slow 10b RO Signaled target abort 0 RO Received target abort 0 RO Received master abort 0 RO Signaled system error 0 RO Detected parity error 0 RO This register a device specific revision identifier 40h RO The register is used to identify the generic function of the RO device and specific register-level programming interface. This register must be implement by master devices that can RW generate the memory write and invalidate command. This register must be implemented as writable by any RW master that can burst more than two data phase. Refer to PCI 2.1 SPEC RO Built in self test RO The register provides an offset into the function's PCI RO configuration space for the location of the first item in the Capabilities linked list When set 01 identifies the linked list item as being the PCI 01 RO power Management registers. This field provide an offset into the function's PCI 0 RO configuration space pointing to the location of next item in the function's capability list A value of 010b indicates that this function complies with 010b RO revision 1.1 of the power management interface specification. PMECLK=1, relies to PCI clock for PME# operation 0b RO PMECLK=0, no PCI clock is require for the function to generate PME#. RO RO RO RO RO
42-43H 42-43H 42-43H 42-43H 42-43H 42-43H
4 5 6-8 9 10 11-15
44-4F
0-31
Reserved DSI The device specific initialization bit AUX_Curr This 3 bit field reports the 3.3Vaux auxiliary current requirement for the PCI function..refer to PM11 Spec D1 Support If this bit a 1,this function support D1 PM state D2 Support If this bit a 1,this function support D2 PM state PME_Supp This 5 bit field indicates the power state in which the function may assert PME#. Bit11 XXXX1b - PME# can be asserted from D0 Bit12 XXX1Xb - PME# can be asserted from D1 Bit13 XX1XXb - PME# can be asserted from D2 Bit14 X1XXXb - PME# can be asserted from D3h Bit15 1XXXXb - PME# can be asserted from D3c PMCSR Refer to Power Management spec 1.0
RWC
Ver_01
19
VIA Technologies, Inc. 4-2. VT6102 INTERNAL REGISTER MAP
PAR3 TCR Reserved IMR1 MAR3 MAR7 PAR2 PAR1 RCR PAR5 Reserved CR1 IMR0 ISR1 MAR2 MAR1 MAR6 MAR5 CURR_RX_DESC_ADDR CURR_TX_DESC_ADDR TFTCMD RFTCMD CURR [8:0]
Preliminary VT6102
PAR0 PAR4 CR0 ISR0 MAR0 MAR4
GFSTATUS
GFTEST BNRY [8:0]
FIFIO DATA PORT Tally counter test port BCR1 BCR0 MIISR PHY_ADR MII DATA REG MIIADR MIICR DEBUG1 DEBUG0 TRST EECSR CFGD CFGC CFGB CFGA Tally Counter_CRC Tally counter_MPA STICKHW PMCPORT MISC.CR Reserved MIMR Reserved MISR Reserved BPMD 0 BPMA [15:0] EE_CHKSUM 0 BPIN_DATA BPCMD 0 SU_PHYID SUSPEND MII_AD 0000_00_0_pauseSR PAUSE TIMER SOFT_TIMER_1 SOFT_TIMER_0 WOLCG.SET TESTREG PWCFG.SET WOLCR.SET WOLCG.CLR TESTREG PWCFG.CLR WOLCR.CLR Reserved PWRCSR.SET Reserved PWRCSR.CLR PATTERN_CRC0 [31:0] PATTERN_CRC1 [31:0] PATTERN_CRC2 [31:0] PATTERN_CRC3 [31:0] BYTEMSK0 [31:0] BYTEMSK0 [63:32] BYTEMSK0 [95:64] BYTEMSK0 [127:96] BYTEMSK1 [31:0] BYTEMSK1 [63:32] BYTEMSK1 [95:64] BYTEMSK1 [127:96] BYTEMSK2 [31:0] BYTEMSK2 [63:32] BYTEMSK2 [95:64] BYTEMSK2 [127:96] BYTEMSK3 [31:0] BYTEMSK3 [63:32] BYTEMSK3 [95:64] BYTEMSK3 [127:96]
00H 04H 08H 0CH 10H 14H 18H 1CH 54H 58H 5CH 68H 6CH 70H 74H 78H 7CH 80H 84H 88H 8CH 90H 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H BCH C0H C4H C8H CCH D0H D4H D8H DCH E0H E4H E8H ECH F0H F4H F8H FCH
Ver_01
20
VIA Technologies, Inc.
4-2-1. VT6102 internal register description (00-07H)
OFFSET Bit 0-63 0
Preliminary VT6102
0-5H 06H 06H 06H 06H 06H
1
2
3
4
06H
5
06H 06H
07H 07H
6 7 0 1
07H 07H 07H 07H
2 3 4 5
Symbol Description PAR0-5 Ethernet address RCR SEP Error Packets Accepted If SEP=0, packet with receive errors are rejected. If SEP=1, packet with receive errors are accepted. AR Small packets Accepted If AR=0,packet smaller than 64 byte are rejected. If AR=1,packet smaller than 64 byte are accepted. AM Multicast packets accepted If AM=0, packet with multicast are rejected. If AM=1, packet with multicast are accepted AB Broadcast Packets Accepted If AB=1,packet with broadcast are accepted. If AB=0,packet with broadcast are rejected. PROM Physical address packets accepted If PROM=0,physical address must match node address in PAR0-5. If PROM=1,all packet with physical destination address are accepted. RRFT0 Receive FIFO Threshold 000-------------64 byte 001-------------32 byte 010------------128 byte 011------------256 byte 100------------512 byte 101------------768 byte 110-----------1024 byte 111------------store & forward RRFT1 RRFT2 TCR RESV Reserved LB0 Transmit Loopback mode 00-------------Normal 01-------------Internal loopback (MAC only) 10-------------MII loopback(MAC-PHY) 11-------------223 or other loopback LB1 OFSET Back-off priority selection
If OFSET =0,VIA back off algorithm If OFSET =1,National specification compatible backoff algorithm
Default ACC RW 0 RW
0
RW
0
RW
0
RW
0
RW
000
RW
0 00b
RW RW
1 0 000
RW RW RW
RESV RTSF0
Reserved Transmit FIFO Threshold (Mode10T) 000------------128 byte------------64byte 001------------256 byte-----------128 byte 010------------512 byte-----------256 byte 011-----------1024byte-----------512 byte 1xx-----------store & forward
07H 07H
6 7
RTSF1 RTSF2
Ver_01
21
VIA Technologies, Inc.
4-2-2.VT6102 internal register description (08-09H)
OFFSET 08H 08H Bit 0 1
Preliminary VT6102
08H
2
08H
3
08H
4
08H
5
08H
6
08H 09H
7 0
09H 09H
1 2
09H
3
09H 09H
4 5
09H
6
09H
7
Description Default ACC CR0 INIT INIT process begin 0 RW 0 RW STRT Start NIC If Start=0,no command entered. If Start=1,start processing a command. 0 RW STOP Stop NIC If Stop=0,command processing is in process If Stop=1,no command processing is in process 0 RW RXON Receive process If RXON=0,no in receive state If RXON=1,turn on the receive DMA state 0 RW TXON Transmit process If TXON=0,no in transmit state If TXON=1, turn on the transmit DMA state 0 RW TDMD Transmit poll demand If TDMD=1,set 1 to poll the TD once, it will be cleared by itself after polling complete. RDMD Receive poll demand 0 RW If TDMD=1,set 1 to poll the RD once, it will be cleared by itself after polling complete. RESV Reserved CR1 EREN Early receive enable 0 RW If EREN=0, disable early receive mode If EREN=1, enable early receive mode. RESV Reserved 0 RW FDX Full duplex 0 RW If FDX=0,set MAC to half duplex mode If FDX=1, set MAC to full duplex mode DPOLL Disable TD/RD auto polling 0 RW If Dpoll=0,set TX/RX auto polling enable. If Dpoll=1,set TX/RX auto polling disable. RESV Reserved 0 RW TDMD1 Transmit poll demand 1 0 RW If TDMD=1,set 1 to poll the TD once, it will be cleared by itself after polling complete. RDMD1 Receive poll demand 1 0 RW If TDMD=1,set 1 to poll the RD once, it will be cleared by itself after polling complete. SFRST Software reset 0 RW If SFRST=0,normal condition If SFRST=1,software reset. It will be cleared after software rest complete. Symbol
Ver_01
22
VIA Technologies, Inc.
4-2-3. VT6102 internal register description (0C-1FH)
OFFSET 0CH 0CH 0CH Bit 0 1 2 Symbol ISR0 PRX PTX RXE Description
Preliminary VT6102
Default ACC
0CH
3
0CH 0CH 0CH 0CH 0DH 0DH 0DH 0DH 0DH 0DH 0DH 0DH 0EH 0FH 10-17H 18-1BH 1C-1FH
4 5 6 7 0 1 2 3 4 5 6 7 0-7 0-7 0-63 0-31 0-31
Received a packet successfully Transmitted a packet successfully Receive error When this bit is set, MAC received with the following errors 1.CRC error 2.Frame alignment error 3.fifo overflow 4.RD linking error. TXE Transmit error When this bit is set, packet transmitted is abort due to 1.excessive collision. 2.Txmit underflow 3.TD linking error TU Transmit buffer underflow RU Receive buffer link error BE PCI Bus error CNT CRC or miss packet tally counter overflow. ISR1 ERI Early receive interrupt UDFI TX FIFO underflow event OVFI Receive FIFO overflow PKT Race FIFO overflow condition, it's mean next packet race with current packet NORBF No more receive buffer to be used ABTI Transmit abort interrupt because of excessive collision SRCI Port state change GENI General purpose Interrupt IMR0 Interrupt mask register 0, all bit correspond to the bits in the ISR0 register. IMR1 Interrupt mask register 1, all bit correspond to the bits in the ISR1 register. MAR0-7 Multicast address Curr_RX_DESC_Address Curr_TX_DESC_Address
0 0 0
RW RW RW
0
RW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Ver_01
23
VIA Technologies, Inc.
4-2-4. VT6102 internal register description (20-2FH)
O0000 Reserved
Preliminary VT6102
Length [10:0] RSR1 RSR0 Reserved RX_Buffer_Size [10:0] C0000 RX DATA BUFFER START ADDRESS RD BRANCH ADDRESS
RDSE0 RDSE1 RDSE2 RDSE3
OFFSET 20H 20H 20H 20H 20H 20H 20H 20H 21H
Bit 0 1 2 3 4 5 6 7 8 9
Symbol RERR CRC FAE FOV LONG RUNT SERR BUFF EDP STP
22-23H 23H 23H
10 11 12 13 14 15 16-26 27-30 31
CHN PHY BAR MAR RESV RXOK Length 0000 O
24-25H
0-10
RBS
26-27H 28-2BH 2C-2FH
11-14 15 16-31 0-31 0-31
0000 C RESV
Description RDSE0-RSR0 Receiver error CRC error Frame alignment error FIFO overflow A Long packet A run packet System error Buffer underflow error RDSE0-RSR1 End of packed buffer Packet start STP EDP 1 1-------- Single buffer descriptor 1 0-------- The start descriptor of chain buffer 0 1-------- The end descriptor of chain buffer 0 0-------- The start middle descriptor of chain buffer Chain buffer NIC accept Physical address packet NIC accept broadcast packet NIC accept multicast packet Reserved Received packed successfully Received packet length Extend byte count for abnormal size Ethernet frame. Owner bit, set by driver at initialization. If OWN=0, descriptor is owed by host. If OWN=1,descriptor is owned by NIC RDSE1 RX_ Buffer Size Receive buffer size for this descriptor, the total byte count of the whole frame will be store in the last descriptor. Must be zero Chain buffer Reserved
Default ACC
RO RO RO RO RO RO RO RO RO RO
1
RO RO RO RO RO RO RO RO RW
RO
RDSE2 RDSE2 RX DATA BUFFER START ADDRESS RDSE3 EDSE3 RD BRANCH ADDRESS
RO RO
Ver_01
24
VIA Technologies, Inc.
4-2-5. VT6102 internal register description (40-4FH)
O Reserved Reserved
Preliminary VT6102
TSR1 TSR0 TCR TX_Buffer_Size [10:0] C0000 TX DATA BUFFER START ADDRESS TDCTL [3:0] TD BRANCH ADDRESS Description TDSE0-TSR0 Collision retry count Experience collision in this transmit event. Reserved Reserved CD hearbeat, this bit only effective in 10base-T mode, when Set this bit indicates a hearbeat collision check failure. TDSE0-TSR1 Transmit abort after excessive collision Out of window collision seen Carrier sense lost when transmitting TX FIFO underflow even. Invalid TD format or structure or TD underflow System error Reserved Transmit error If TERR=0,transmit successful If TERR=1,excessive collision (COL16TM) Reserved Owner bit, set by driver at initialization. If OWN=0, descriptor owned by host. If OWN=1,descriptor owned by NIC TDSE1 TX_ Buffer Size Transmit packet buffer size for this descriptor, the total byte count of the whole frame will be store in the last descriptor. Extend fragment of frame length, must be zero. Chain buffer TDSE1-TCR Disable CRC generation Reserved Start of transmit packet End of transmit packet Assert interrupt immediately while the descriptor has been Send complete. Reserved TDSE2 TX DATA BUFFER START ADDRESS TDSE3 If this bit set to 0, issue interrupt for this packet If this bit set to 1, no interrupt generated Received TD BRANCH ADDRESS
TDSE0 TDSE1 TDSE2 TDSE3
OFFSET 40H
Bit 0-3 4 5 6 7
Symbol NCR0-3 COLS RESV RESV CDH
Default ACC
RO RO RO RO RO
41H
8 9 10 11 12 13 14 15
ABT OWC CRS UDF TBUFF SERR RESV TERR
RO RO RO RO RO RO RO RO
42-43H
16-30 31
RESV O
RO RW
44-45H
0-10
TBS
RO
44-45H 44-45H 46-47H
11-14 15 16 17-20 21 22 23 24-31
0000 C CRC RESV STP EDP IC RESV TDSE2 TDCTL TDCTL TDSE3
RO RO RO RO RO RO RO RO RO RO RO RO
48-4BH 4CH 4CH 4C-4FH
0-31 0 1-3 4-31
Ver_01
25
VIA Technologies, Inc.
4-2-6. VT6102 internal register description (6C-6FH)
OFFSET Bit Symbol
Preliminary VT6102
6CH
0-4
PHYAD
6CH
5
MFDC
6CH 6CH
6 7
MPO0 MPO1
6DH
0
SPD10
6DH
1
LNKFL
6DH 6DH 6DH
2 3 4
RESV MIIERR PHYOPT
6DH 6DH 6DH 6EH 6EH 6EH
5 6 7 0 1 2
RESV RESV PHYRST DMA0 DMA1 DMA2
6EH 6EH 6EH 6EH 6EH 6FH 6FH 6FH 6FH 6FH 6FH
3 4 5 6 7 0 1 2 3 4 5
CRFT0 CRFT1 CRFT2 EXTLED MED2
POT0 POT1 POT2 CTFT0 If CTFT2,CTFT1,CTFT0=0,0,0 then TXFIFO threshold CTFT1 control is determined by TCR, else it is determined by CTFT2 BCR1
Default ACC Description PHY_ADR 00001b RW Extend PHY device address These register bytes store from EEPROM loading when power up or EEPROM auto-reloading , it's can be programmed by software. 0 RW Accelerate MDC speed If MFDC=0,MDC=normal If MFDC=1,MDC=4X accelerating 00 RW MII management polling timer interval 00-----------------1024 MDC clock cycles 01------------------512 MDC clock cycles 10------------------128 MDC clock cycles 11--------------------64 MDC clock cycles MIISR 1 RW PHY Speed If SPD10=0, speed at 100MB If SPD10=1, speed at 10 MB 1 RW Link Fail If LNKFL=0, link success. If LNKFL=1, link fail that no cable is connect. Reserved 0 RW PHY device received error. 0 RW 1 RW PHY option If PHYOPT=0, PHY address will be update by EEPROM If PHYOPT=1, use default PHY address as 0001b. Reserved 0 RW Reserved 0 RW PHY reset, by software driven. 0 RW BCR0 RW DMA Length 0 000-----------------32 byte-----------------8 DW 001-----------------64 byte---------------16 DW 010----------------128 byte---------------32 DW 011----------------256 byte---------------64 DW 100----------------512 byte--------------128 DW 101---------------1024 byte--------------256 DW 110---------------store & forward 111---------------store & forward If CRFT2,CRFT1,CRFT0=0,0,0 then RXFIFO threshold RW 0 control is determined by RCR, else it is determined by BCR0 Extra LED support control RW 0 Medium select control RW 0 BCR1 Polling timer interval. RW 0
0
RW
Ver_01
26
VIA Technologies, Inc.
4-2-7. VT6102 internal register description (70-77H)
OFFSET Bit Symbol
Preliminary VT6102
70H 70H 70H 70H 70H 70H 70H 70H
0 1 2 3 4 5 6 7
MDC MDI MDO MOUT MDPM WCMD RCMD MAUTO
71H 71H 71H 71H 71H 71H
0 1 2 3 4 5
71H 71H 74H 74H 74H 74H 74H 74H 74H 74H 75H 76H 77H
6 7 0 1 2 3 4 5 6 7 0-7 0-7 0-7
MAD0 MAD1 MAD2 MAD3 MAD4 MDONE A pause status/control bit, when MDIO auto polling data is ready, It's mean MII state of SM is at the end of a auto polling cycle. MSRCEN If MSRCEN=1, close the pause function of MDONE MIDLE If MIDLE=1, has not at MII auto polling cycle. EECSR EDO Direct program EEPROM interface data out status EDI Direct program EEPROM interface data in status ECK Direct program EEPROM interface clock status ECS Direct program EEPROM interface chip select status DPM Direct program EEPROM mode AUTOLD Dynamic reload EEPROM content, the Ethernet ID will be updated. EMBP EEPROM embedded program enable, reset while programming complete EEPR EEPROM programmed status, 73H indicate programmed. TEST TEST mode register DEGUG0 Debug mode 0 DEGUG1 Debug mode 1
Default ACC Description MIICR Direct programming status as management port clock RW Direct programming input while read PHY status RW Direct programming status as management port data out RW MDIO out put enable indicator. RW RW Direct PHY programming mode enable If MDPM=1,WCMD & RCMD have no effect Write enable to write PHY, reset while write complete RW Read enable to read PHY, reset while read complete and PHY RW Status is store in 0x72H RW MII management port auto polling enable. MIICR has no effect while MAUTO=1 MIIADR MII management port address bit [4:0] 0001b RW
RW
RW RO RO RW RW RW RW RW RW RO RW RW RW
Ver_01
27
VIA Technologies, Inc.
Preliminary VT6102
4-2-8. VT6102 internal register description (78-7BH) Default ACC OFFSET Bit Symbol Description CFG_A 78H 0-5 RESV Reserved RW 78H 6 MIIOPT If MIIOPT=0,without extension clock. RW If MIIOPT=1, with extension clock. 78H 7 EELOAD Enable EEPROM embedded and direct programming , RW always 0 after power on and loading. CFG_B 79H 0 LATMEN Latency timer RW If LATMEN=0, Latency timer disable. If LATMEN=1, Latency timer enable 79H 1 MWAIT Master write insert one wait state 2-2-2-2 RW 79H 2 MRWAIT Master read insert one wait state 2-2-2-2 RW RXARBIT Arbitration priority select. 79H 3 RW The receive FIFO DMA will be interleave to transmitting FIFO DMA after 32 DWORD transaction 79H 4 TXARBIT The transmitting FIFO DMA will be interleave to RW Receiving FIFO DMA after 32 DWORD transaction 79H 5 MRLDIS Memory read line support RW If MRDLDIS=0, memory read line support If MRDLDIS=1, disable memory read line support 79H 6 PERRDIS Disable data parity generation and checking RW 79H 7 QPKTDIS Disable transmit frame queuing. RW CFG_C 000b RW 7AH 0 BPS0 BOOTROM size select 7AH 1 BPS1 000----------no BOOTROM 7AH 2 BPS2 001----------- 8K size 010----------16K size 011----------32K size 1xx----------64K size 7AH 3 BTSEL BOOTROM timing select RW 7AH 4 RESV Reserved RW 7AH 5 DLYEN Turn on delay transaction while memory read bootrom. RW 7AH 6 BROPT Tie the unused bootrom address MA to high RW 7AH 7 MED3 Medium select control RW CFG_D 7BH 0 BAKOPT Backoff algorithm optional 0 RW If BAKOPT=0,disable Backoff algorithm optional If BAKOPT=1,enable Backoff algorithm optional 7BH 1 MBA Capture effect solution selection -1 for AMD solution 0 RW 7BH 2 CAP Capture effect solution select-2 for DEC solution 0 RW CRADOM Backoff algorithm random. 7BH 3 0 RW 7BH 4 PMCDIG PMCC(0x82) setting test mode, while PMCCDIG=1 can 0 RW be read/write. 7BH 5 MRLEN PCI memory read line capable. 0 RW If MRLEN=0, no capable. If MRLEN=1, capable. 7BH 6 DIAG Diagnostic mode 0 RW If DIAG=0, disable. If DIAG=1, enable . 7BH 7 MMIOEN Memory mapped IO access enable. 0 RW 4-2-9. VT6102 internal register description (80-8BH)
OFFSET Bit Symbol Description MISC.CR
Default ACC
Ver_01
28
VIA Technologies, Inc.
80H 80H 0 1
Preliminary VT6102
RW RW
80H 80H 80H 81H 81H 81H 81H 81H 83H 83H 83H 83H 83H 83H
2 3 4-7 0 1-4 5 6 7 0 1 2 3 4-6 7
84H 84H 84H 84H 84H 84H 84H 84H 85H 86H 86H 86H 86H 86H 86H 86H 86H 87H 88-8BH
0 1 2 3 4 5 6 7 0-7 0 1 2 3 4 5 6 7 0-7 0-31
Tm0EN Enable software timer 0 to count Tm0Susp Tm0susp will be set 1, when SoftTimer0 time out When SW clear Tm0susp to 0, SoftTimer0 will continue to Count. HDXFEN Half-duplex flow control enable FDXRFEN Full-duplex flow control RX enable RESV Reserved Tm1EN Enable software timer 1 to count RESV Reserved VAXJMP There is a AUX power outside, for software reference FORSRST Force software reset RESV Reserved STICKHW DS0 Sticky DS0_shadow,suspend well DS write port DS1 Sticky DS1_shadow, R/W by software WOLEN Legacy WOL enable WOLSR Legacy WOL status RESV Reserved LGWOL Legacy WOL enable ,status for software reference from jumper strapping MD5. MISR TM0INT Software timer o interrupt TM1INT Software timer 1 interrupt RESEV Reserved TDWBR TD WB queue race, will cause when TX shut down. SSRCI Suspend well MII polling status change interrupt. UDPIS User defined, host driven interrupt UDPI User defined, host driven interrupt PWEI Power event report in test mode RESV Reserved MIMR TM0IM Software timer o interrupt mask TM1IM Software timer 1 interrupt mask RSEV Reserved TDWBIM TD WB queue race, will cause when TX shut down mask SSRCIM Suspend well MII polling status change interrupt, by diagnosis use mask 0 User defined, host driven interrupt mask UDPIM User defined, host driven interrupt mask PWEIM Power event report in test mode mask RESV Reserved RESV Reserved
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Ver_01
29
VIA Technologies, Inc.
4-2-10. VT6102 internal register description (8C-A7H)
OFFSET Bit Symbol Description BPMA[15:0] Flash address port [15:0] Reserved Flash write data output port BPCMD BOOTROM embedded read command BOOTROM embedded write command Reserved Flash write data output port Reserved EE_CHKSUM MII address at suspend well
Preliminary VT6102
Default ACC
8C-8DH 8EH 8FH 90H 90H 90H 91H 92H 93H 94-95H 96H 97H 98-99H 9A-9BH 9C-9DH 9E-9FH A0/A4H A0/A4H A0/A4H A0/A4H A0/A4H A1/A5H A1/A5H A1/A5H A1/A5H A1/A5H A1/A5H A1/A5H A2/A6H A2/A6H A3/A7H A3/A7H A3/A7H A3/A7H A3/A7H A3/A7H A3/A7H
0-15 0-7 0-7 0 1 2-6 0-7 0-7 0-7 0-15 0-7 RESV 0-15 0-15 0-15 0-15 0-3 4 5 6 7 0 1 2-3 4 5 6 7 0 1-7 0-1 2 3 4 5 6 7
BPMA RESV BPMD EBPRD EBPWR RESV BPIN RESV CHKSUM Suspend MII_AD 0-7
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
SU_PHYID PHY address at suspend well
PTNMH UNICAST
MAGICEN
LinkON LinkOFF WOLEN WOLSR RESV LEGCY WOL
Reserved Pause timer PauseSR Soft timer_0 period Soft timer_1 period WOLCR.SET / WOLCR.CLR PTNMH[3:0] enable pattern match filtering Enable UNICAST filter. Enable Magic packet filter. Enable link on detected . Enable link off detected. PWCFG.SET /PWCFG.CLR Legacy WOL_EN shadow Legacy WOL_SR shadow Reserved Enable legacy wake on lan
WOLTYPE Drive WOL output by pulse(1) or button (0) RESV Reserved SMIITIME Internal MII interface timing
TESTREG.SET / TESTREG.CLR SNORM All power state capable while PHYTEST=0 RESV Reserved WOLCG.SET / WOLCG.CLR RESV Reserved SMIIOPT MIIOPT to extend clock in suspend well SMIIACC MDC acceleration SAB Accept broadcast in suspend well SAM Accept multicast in suspend well SFDX Full duplex in suspend well PMEOVR For legacy use, force PMEEN always over PME_EN
Ver_01
30
VIA Technologies, Inc.
4-2-11. VT6102 internal register description (B0-FFH)
OFFSET Bit Symbol Description PATTERN CRC0-CRC3 PATTERN CRC0 PATTERN CRC1 PATTERN CRC2 PATTERN CRC3 BYTEMSK 0-3 BYTEMSK 0 BYTEMSK 1 BYTEMSK 2 BYTEMSK 3
Preliminary VT6102
Default ACC
B0-B3H B4-B7H B8-BBH BC-BFH C0-CFH D0-DFH E0-EFH F0-FFH
0-31 0-31 0-31 0-31 0-127 0-127 0-127 0-127
CRC0 CRC1 CRC2 CRC3 Bytemsk Bytemsk Bytemsk Bytemsk
RW RW RW RW RW RW RW RW
Ver_01
31
VIA Technologies, Inc.
Preliminary VT6102
5. ELECTRICAL SPECIFICATION
5-1. ABSOULTE MAXIMUN RATING
Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Rating Min 3.0 -0.5 -0.5 -65 0 Max 3.6 Vcc+0.5 Vcc+0.5 150 70 2500 Unit Volts Volts Volts J J Volts
Note: Stress above the conditions listed may cause permanent damage to the device Functional operation of this device should be restricted to the conditions described Under operating conditions.
5-2. DC SPECIFICATIONS
TA-0-70 JVcc =3.3V , Symbol ICC ICCIDLE ICCLP VIL VIH IIL VOL VOH VOLM VOHM VOL IOZ Parameter Supply Current - Average Active Supply Current - Average Idle Supply Current - Low Power Mode Input Low Voltage Input High Voltage Input Leakage Current
Output Low Voltage - High Drive Outputs Output High Voltage - High Drive Outputs
Output Low Voltage - MOS Outputs Output High Voltage - MOS Outputs Output Low Voltage - O.C. Output
Tristate Leakage Current
Min -0.5 2.0 -1.0 2.4 -10
Max 100 80 35 0.8
Vcc+.05
+1.0 0.5 0.1 Vcc-0.1 0.5 +10
Unit mA mA mA V V uA V V V V V uA
Condition X1=25Mhz, VIN switching X1=25Mhz, VIN=Vcc or GND X1 undriven, VIN=Vcc or Undriven
GNDNote: These parameters are not guaranteed by production testing, All electrical specification are based on IEEE 802.3 requirements and internal design considerations.
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VIA Technologies, Inc.
Preliminary VT6102
6. TIMING SPECIFICATION
6-1. PCI BUS MASTER
1.All of the timing are captured from verilog simulation with three cases : Best/Normal/Worst 2.PCICLK = 33MHz 6-1-1. Get TX descriptor
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccc hfllllllllrhh znxdddxxxxozz znxdddddddozz hhflllllllkhh hhhhhhflllrhh \@+ tirval @+ tfval @+ tadval, tcbeval @+ tfhold @$. tirhold
Width (ns) (7.2, 10.6, 18.7) min:( 7.7, 11.1, 20.0), max:( 8.6, 12.7, 22.3) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.2) ( 6.9, 10.2, 18.0) ( 3.2, 4.8, 8.4) Note
Symbol Parameter tfval PCICLK rising edge to FRAME# Valid Delay tadval PCICLK rising edge to AD[31:0] Valid Delay tcbeval PCICLK rising edge to CBE[3:0] Valid Delay tirval PCICLK rising edge to IRDY# Valid Delay tfhold FRAME# hold time tirhold IRDY# hold time Note : 1.(xxx, xxx, xxx) : (best, normal, worst) 2.FRAME# hold time for frame#=0 to frame#1 3.IRDY# hold time for frame#=0 to frame#1
2. 3.
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VIA Technologies, Inc.
6-1-2. Get RX descriptor
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccc hfllllllllrhh znxdddxxxxozz znxdddddddozz hhflllllllkhh hhhhhhflllrhh \@+ tirval @+ tfval @+ tadval, tcbeval @+ tfhold @$. Tirhold
Width (ns) (7.2, 10.6, 18.7) min:( 7.7, 11.1, 20.0), max:( 8.6, 12.7, 22.3) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.2) ( 7.0, 10.3, 18.2) ( 3.2, 4.8, 8.4) Note
Symbol Parameter tfval PCICLK rising edge to FRAME# Valid Delay tadval PCICLK rising edge to AD[31:0] Valid Delay tcbeval tirval tfhold tirhold Note : 1.(xxx, xxx, xxx) : (best, normal, worst) 2.FRAME# hold time for frame#=0 to frame#1 3.IRDY# hold time for frame#=0 to frame#1 PCICLK rising edge to CBE[3:0] Valid Delay PCICLK rising edge to IRDY# Valid Delay FRAME# hold time IRDY# hold time
2. 3.
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VIA Technologies, Inc.
6-1-3. Write back status to descriptor
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccc hfrhhhhhhh znxddddozz znxddddozz hhfllllkhh hhhhhhfrhh \@+ tirval,tfhold @+ tfval @+ tadval, tcbeval @+ @+ tdaval tdahold @$. Tirhold
Width (ns) ( 7.2, 10.6, 18.7) ( 7.7, 11.4, 20.0) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.3) ( 5.7, 8.4, 14.8) ( 7.2, 10.6, 18.7) ( 5.7, 8.4, 14.8) (5.2, 7.6, 13.4) ( 3.2, 4.8, 8.4) Note
Symbol tfval tadval tcbeval tirval tfhold tdaval tfhold tdahold tirhold Note :
Parameter PCICLK rising edge to FRAME# Valid Delay PCICLK rising edge to AD[31:0] Valid Delay PCICLK rising edge to CBE[3:0] Valid Delay PCICLK rising edge to IRDY# Valid Delay FRAME# hold time PCICLK rising edge to AD[31:0](data) Valid Delay FRAME# hold time AD[31:0] hold time IRDY# hold time
1.(xxx, xxx, xxx) : (best, normal, worst)
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VIA Technologies, Inc.
6-1-4. Read data into FIFO
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccccccccccc hblllllllllllllllkhhh znxddddxxxozzzznxxxoz znxdddddddozzzzndddoz hhflllllllkhhhhflllkh hhhhhhfllllllllllllkhh \@+ tirval0 @\+tirh0 @+tirval@\; tirh1 @+ tfva1 @\; tfh
Width (ns) ( 7.2, 10.6, 18.7) ( 6.9, 10.2, 17.9) ( 4.7, 7.0, 12.3) ( 4.8, 7.0,12.4) ( 3.5, 5.1, 8.9) ( 3.2, 4.8, 8.4) min( 7.7, 11.4, 20.0), max( 9.5, 13.9, 24.5) ( 4.7, 7.0, 12.3) Note
Symbol tfval tfh tirval0 tirval1 tirh0 tirh1 tadval
Parameter PCICLK rising edge to FRAME# Valid Delay FRAME# hold time PCICLK rising edge to IRDY# Valid Delay PCICLK rising edge to IRDY# Valid Delay IRDY# hold time IRDY# hold time PCICLK rising edge to AD[31:0] Valid Delay
tcbeval PCICLK rising edge to CBE[3:0] Valid Delay Note : 1.(xxx, xxx, xxx) : (best, normal, worst)
Ver_01
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VIA Technologies, Inc.
6-1-5. Write data from FIFO
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccccccccccc hfllllllllllllllllrhh znxddddxxxozzzznxxxoz znxdddddddozzzzndddoz hhflllllllkhhhhflllkh hhhhhhfllllllllllllrh @+ tfval @; tdah0 \\\\\@\; tfh \@+ tirval0 \\\\\@\; tirval1 \@+ tdava10 @$. tirh0 \\\@ $. tirh1 @+ tadval, tcbeval @+ tdah1 @+tdaval1 @+ tdah2
Width (ns) ( 7.2, 10.6, 18.7) Min.( 6.8, 9.9, 17.5) Max( 7.6, 11.2, 19.7) ( 4.7, 7.0, 12.3) ( 5.3, 7.9, 13.8) Min( 7.7, 11.4, 20.0) Max( 9.5, 13.9, 24.5) ( 4.7, 7.0, 12.2) ( 4.0, 5.8, 10.3) ( 3.2, 4.8, 8.4) Min( 4.9, 7.2, 10.7) Max( 7.2, 10.6, 18.6) Min.( 5.1, 7.6, 13.3) Max( 7.7, 11.1, 19.5) Min.( 4.3, 6.4, 11.2) Max.( 7.4, 10.9, 19.2) Min.( 4.3, 6.4, 11.2) Max.( 5.1, 7.6, 11.5) Min.( 4.3, 6.5, 11.5) Max.( 5.2, 7.9, 13.4) Note
Symbol Parameter tfval PCICLK rising edge to FRAME# Valid Delay tfh FRAME# hold time tirval0 tirval1 tadval tcbeval tirh0 tirh1 tdaval0 PCICLK rising edge to IRDY# Valid Delay PCICLK rising edge to IRDY# Valid Delay PCICLK rising edge to AD[31:0] Valid Delay PCICLK rising edge to CBE[3:0] Valid Delay IRDY# hold time IRDY# hold time PCICLK rising edge to data Valid Delay
tdaval1 PCICLK rising edge to data Valid Delay tdah0 tdah1 tdah2 Data hold time Data hold time Data hold time
Note : 1.(xxx, xxx, xxx) : (best, normal, worst)
Ver_01
37
VIA Technologies, Inc. 6-2. PCI BUS SLAVE
6-2-1. IO read/write
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccc hfrhhhhhhhhhh znondddddozzz znxddddddozzz hhfllllllkhhh hhhhhhhhfrhhh \\@+ tdaval @+ tdah @+ ttrval, @+ ttrhold
Width (ns) Max.( 8.2, 12.1, 21.3) Min( 5.8, 8.5, 15.0) Max( 8.4, 12.1, 21.9) Min( 5.8, 8.5, 15.0) ( 4.6, 6.7, 11.8) ( 3.1, 4.6, 8.2) Note 2 2
Symbol Parameter tdaval PCICLK rising edge to DATA Valid Delay tdah ttrval ttrh DATA hold time PCICLK rising edge to TRDY# Valid Delay TRDY# hold time
Note : 1.(xxx, xxx, xxx) : (best, normal, worst) 2. IO read only
Ver_01
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VIA Technologies, Inc.
6-2-2. Cfg read/write
Preliminary VT6102
PCICLK FRAME# AD[31:0] CBE#[3:0] IRDY# TRDY#
ccccccccccccc hfrhhhhhhhhhh znondddddozzz znxddddddozzz hhfllllllkhhh hhhhhhhhfrhhh \\@+ tdaval @+ tdah @+ ttrval, @+ ttrhold
Width (ns) ( 8.2, 12.1, 21.3) ( 5.8, 8.5, 15.0) ( 4.6, 6.7, 11.8) ( 3.1, 4.6, 8.2) Note 2 2
Symbol tdaval tdah ttrval ttrh
Parameter PCICLK rising edge to DATA Valid Delay DATA hold time PCICLK rising edge to TRDY# Valid Delay TRDY# hold time
Note : 1.(xxx, xxx, xxx) : (best, normal, worst) 2.Cfg read only
Ver_01
39
VIA Technologies, Inc. 6-3. MII
6-3-1. MII TX
Preliminary VT6102
MTXC MTXE MTXD[3:0]
ccccc//cccccc lrhhh//hhhhhf znxxx//xxxxxo @+ttxeval, ttxdval0 @+ ttxeh, ttxdh, @+ ttxdval1
Width (ns) ( 3.7, 5.4, 9.5) ( 3.6, 5.3, 9.3) Min.( 3.5, 5.1, 8.9) Max.( 5.8, 8.6, 15.1) ( 5.9, 8.7, 15.3) ( 5.7, 8.4, 14.7) Note
Symbol Parameter ttxeval PCICLK rising edge to TXE Valid Delay ttxdval0 PCICLK rising edge to TXD Valid Delay ttxdval1 PCICLK rising edge to TXD Valid Delay ttxeh ttxdh Note : 1.(xxx, xxx, xxx) : (best, normal, worst) TXE hold time TXD hold time
6-3-2. MII MDIO
MDC cccccccccccccccccccc//cccccccc MDIO hfrfrfrhflllllllrfll//lllllrhh
All of MDIO signals transition occure in negative egde of MDC.
Ver_01
40
VIA Technologies, Inc. 6-4. BOOTROM
6-4-1. One Dword bootrom access timing (with delay transaction)
Preliminary VT6102
PCICLK cccccccccccccccccccccccccccccccccccccccccc FRAME# frhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh IRDY# hfllllllllllllllllllllllllllllllllllllkhhh TRDY# hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhfkhhh BPRD# hhhhhflllrhhhflllrhhhflllrhhhflllrhhhhhhhh MA zzzmddddddomddddddomddddddomddddddozzzzzzz MD zzzzzz<" ddozzz<" ddozzz<" ddozzz<" ddozzzzzzz ; tfb ?. tbp? $.?tab +?tba + tbb z? +z tbt @'
Symbol Parameter tfb The PCLK rising edge which latches FRAME# to BPRD# is asserted tab tbp tba tbb tbt MA ready to BPRD# asserted BPRD# is asserted BPRD# deasserted to MA deasserted BPRD# is deasserted between two one byte bootrom cycle BPRD# is deasserted to the PCLK rising edge which latches TRDY#
max (ns)
min (ns) (485, 487, 492) (29.5, 29.4, 28.9) (299,298,298) (DTSEL=0) (29.7, 29.5, 29.2) (510, 511, 512) (145, 143, 139)
Note 2
(509, 508, 508) (DTSEL=1)
3,
Note : 1.Delay transaction control bit : PCI cfg/7ah/bit5 2.(xxx, xxx, xxx) : (best, normal, worst) 3.DTSEL : PCI cfg/7ah/bit4
Ver_01
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VIA Technologies, Inc.
6-4-2. One Dword bootrom access timing (without delay transaction)
Preliminary VT6102
PCICLK ccccccccccccccccccccccccccccccccccccccccccccc FRAME# frhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhhfrhhhhhh IRDY# hflllkhhhflllkhhhhhhhhhhhhhhhhhhhhhhhhflllllk TRDY# hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhfr STOP# hhhhfkhhhhhhfkhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh BPRD# hhhhhflllrhhhflllrhhhflllrhhhflllrhhhhhhhhhhh MA zzzmddddddomddddddomddddddomddddddozzzzzzzzzz MD zzzzzz<" ddozzz<" ddozzz<" ddozzz<" ddozzzzzzzzzz STOP# hhhhfrhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh ;zzzzzzzzzzzz tff zzzzzzzzz@' \\\@+ tsval @+
tsh
(ns) min (3300, 3300, 3300) ( 5.4, 8.0, 14.1) ( 3.8, 5.6, 9.8) Note
Symbol Parameter tff The initial FRAME# to the second valid FRAME# tsval PCICLK rising edge to STOP# Valid Delay tsh STOP# hold time
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VIA Technologies, Inc.
6-4-3. Embedded Flash Cycle Timing
Preliminary VT6102
A. Flash Write Timing, WE# controlled only:
!z?TAS +zz TAH zz? MA[15:0]zzndddddddddddddddozzz BPCS# hhhhflllllllllllrhhhhh BPWR# hhhhhhhhflllllrhhhhhhh MD[7:0] zzzzzzzndddddddozzzzzz +z TDS z? +z TWP @+?TDH
Symbol TAS TAH TWP TDS TDH
Parameter Address Setup Time Address Hold Time BPWR# Pulse Width Data Setup Time Data Hold Time
Timing 116 423 270 298 61
Unit ns ns ns ns ns
B. Flash Read Timing:
+zzzzz TAA zzzzz? +z TAS @;z TRP z? MA[15:0]zzndddddddddddddddozzz BPCS# hhhhflllllllllllrhhhhh BPRD# hhhhhhhhflllllrhhhhhhh MD[7:0] zzzzzzzzzznddddozzzzzz +z?TRD +?TDH
Symbol TAS TAA TRP TRD TDH
Parameter Address Setup Time Address Cycle Time BPRD# Pulse Width Read Access Time Data Hold Time
Timing 85 508 330 230(max) 0 (max)
Unit ns ns ns ns ns
Ver_01
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VIA Technologies, Inc.
Preliminary VT6102
7. APPLICATION SCHEMATIC
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VIA Technologies, Inc.
Preliminary VT6102
Ver_01
46
VIA Technologies, Inc.
Preliminary VT6102
8. Package Mechanical Specifications
Ver_01
47

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